An ongoing challenge in integrated circuit (IC) technology comprises the removal of thermal heat generated by active components of the integrated circuit, especially when the integrated circuit has high current requirements, such as in a high-current quad flat pack no-lead (QFN) integrated circuit package. Pressure in the industry continues to demand increased densities of device integration, as well as diminished component feature sizes, therein increasing densities of power and thermal energy generation. However, in order to maintain the active components at their optimum (low) operating temperatures and speed, this heat must be continuously dissipated and removed to outside heat sinks. Unfortunately, this effort becomes increasingly more difficult as the energy density becomes progressively greater.
One effective approach to remove heat in conventional packages focuses on thermal transport through the thickness of the semiconductor chip from the active surface to the passive surface. FIG. 1 illustrates a conventional semiconductor package 10, comprising a semiconductor chip 12 having an active surface 14 and a passive surface 16. Active components (not shown) positioned on the active surface 14 of the semiconductor chip 12 are typically bonded to individual leads 18 of a metallic leadframe 20 via bond wires 22, and the semiconductor chip is further encapsulated by a plastic encapsulation device 24 to protect the chip and associated wire bonds.
The passive surface 16 of the semiconductor chip 12 is attached to a chip mount pad 26 of the metallic leadframe 20, wherein the thermal energy from the integrated circuit can flow into the chip mount pad of the metallic leadframe. When properly formed, this leadframe 20 can act as a heat spreader to an outside heat sink (not shown, but typically provided on a printed circuit board, to which the semiconductor package is mounted). In many semiconductor package designs, this implies a portion 28 of the leadframe 20 protruding from the plastic encapsulation device 24 such that it can be directly attached to the outside heat sink. Examples are described in U.S. Pat. No. 5,594,234, issued on Jan. 14, 1997 (Carter et al., “Downset Exposed Die Mount Pad Leadframe and Package”) and U.S. Pat. No. 6,072,230, issued on Jun. 6, 2000 (Carter et al., “Bending and Forming Method of Fabricating Exposed Leadframes for Semiconductor Devices”).
From a standpoint of thermal efficiency, these approaches have several shortcomings. For example, the heat generated by active components must traverse the macroscopic thickness of the semiconductor chip 12 in order to exit from the chip through the leadframe 20. The heat further faces the thermal barrier of the die attach material that couples the chip 12 to the mount pad 26 (typically a polymer) before it can enter the leadframe 20. Further, a technical solution is missing to remove the heat generated by active components directly from the IC into a metallic heat conductor and heat spreader positioned in microscopic proximity to the active component on the active surface 16. In the typical package 10, the heat is first spread through the macroscopic thickness of the molding material 24 (typically an epoxy filled with inorganic particles, a mediocre thermal conductor) and only then is the heat spread into a metallic heat spreader (not shown), usually positioned on a surface 30 of the molded package 10.
QFN packages are similar to the conventional package 10, however, the leads 18 of the conventional package are integrated into the package, as illustrated in FIG. 2. The QFN package 40 again comprises a chip 42 having an active surface 44 and a passive surface 46. Active components (not shown) positioned on the active surface 44 of the semiconductor chip 42 are conventionally bonded to integrated leads 48 of a metallic leadframe 50 via bond wires 52, and the semiconductor chip is again encapsulated by an encapsulation device 54 to protect the chip and associated wire bonds. Similar to the conventional package 10 of FIG. 1, the conventional QFN package 40 of FIG. 2 also suffers from a mediocre transfer of heat from the active surface 44 of the chip 42 during operation, since the a heat sink cannot be placed proximal to the active surface. Heat is conventionally transferred through the thickness of the chip 42 and then through the passive surface to a customer-supplied circuit board or other device, which may or may not further comprise an external heat sink.
The thermal situation is likewise difficult in a conventional ball-grid (or land-grid) array package. A typical BGA package 60 is illustrated in FIG. 3, wherein the BGA package generally comprises an IC chip 62 mounted to a multi-layer substrate 64 (e.g., a circuit board), wherein the substrate acts as a heat spreader 66. The IC chip 62 may be further enclosed by a metal cap 68 or a mold compound (not shown), thus mechanically protecting the IC chip from external forces. The IC chip 62 is generally mounted on the substrate 64 via a plurality of solder balls 70, wherein the solder balls electrically connect the small bond pads 72 of the IC chip to the bond pads 74 on the substrate, while also acting as a thermal path to dissipate thermal energy away from the IC chip. The thermal path, however, is limited through the solder balls 70, since the size of the solder balls is small relative to the distance required for thermal energy dissipation. Furthermore, the size of the solder balls also limits the current that can be passed between the IC chip and the substrate. A QFN package utilizing such a conventional BGA design, therefore, is greatly limited in the amount of current that can pass through the solder balls, as well as in terms of heat transfer through the solder ball connection to the circuit board.
Therefore, a need currently exists for a thermally improved, high power high electrical current QFN package structure. Further, a reliable and cost-effective method for producing the QFN package is desirable, wherein the resulting package should not only meet high thermal and electrical performance requirements, but the manufacture of same should also achieve improvements towards the goals of enhanced process yields and device reliability.